A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM
نویسندگان
چکیده
This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed is enough in bit-interleaving architecture to enhance soft-error immunity combined error correction code. read stability of the improved by decoupled. writability data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on standard 55nm CMOS technology show that static noise margin 16.13x as conventional 6T bitcell. Moreover, failure region eliminated. In addition, leakage consumption 15.7% compared
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2022
ISSN: ['1349-2543', '1349-9467']
DOI: https://doi.org/10.1587/elex.19.20220089